Products

Lightspeed Logic's mask-reconfigurable IP is the best solution available to both fabless and IDM semiconductor manufacturers confronted by SoC integration issues, shortening market windows, and increased deep-submicron technology challenges.

• Standard tile based reconfigurable logic — Lightspeed Logic provides standard products based on TSMC’s 130nm, 90nm, and 65nm technologies. Additionally, Lightspeed Logic technology is available from several IDMs.
• Manufacturability Optimized Tile — Provide optimum results over a wider range of design styles by allowing drive-strength mutability as well as the ability to have some percentage of the cells being used for flip-flops to be used for combinational functions when not needed as a sequential function.
• Reconfigurable I/Os — Silicon-proven in TSMC’s 130nm process. Lightspeed Logic can support single-ended only I/O, differential only I/O, or a twin-pad design that supports either single-ended or differential standards.

Lightspeed Logic's Advantages

• Density — Our customers enjoy a significant logic density and performance advantage vs. the solutions offered by our competitors. Lightspeed Logic provides the best arrayed logic density in the industry, approaching that of traditional standard cell.
• Unit cost — Achieves the lowest unit cost available for deep submicron synthesizable logic. As an array-based logic solution, decreases defect density substantially. This increased yield in combination with industry leading logic density results in the lowest COGS of any synthesizable logic solution available to the market.
• Proven performance — Lightspeed Logic’s fourth- and fifth-generation architectures build upon a proven track record of successful reconfigurable logic architectures on which hundreds of designs have been developed and shipped to customers worldwide.
• Variable customization layers —Supports variations from two metal, two via through six metal, six via customization.
• Time — Reduces time-to-market vs. traditional standard cell design; especially for derivative devices.
• Testing — Support for scan insertion is standard.

EDA Flow

As a partner with leading EDA vendors, Lightspeed Logic has developed to work in a traditional EDA flow. Our partners include:

• Cadence OpenChoice
• Magma MagmaTies
• Synopsys

Customer Applications

• ASSP SoCs and ASIC SoCs use our reconfigurable logic and I/Os to implement rapidly evolving new technologies, standards or customer IP. This allows for adjustment to new algorithms, regulatory requirements, or embedding customer-specific IP.
• Platform SoC product families use our reconfigurable logic for features that differ from product family member to product family member, including features requested by customers, or supporting different vertical markets.
• ICs implemented with our IP mitigate deep sub-micron related device failures, providing substantially higher working first silicon results and higher manufacturing yields.

Available Process Nodes

• 150nm — IDM version in use now
• 130nm — Foundry versions available now
• 90nm — Various IDM versions in use and under development now
• 65nm — Various IDM versions in use and under development now
• 45nm — IDM versions in development now

As an IPnow partner of ARM/Artisan, Lightspeed Logic is pleased to offer Reconfigurable Logic for any process for which Artisan standard cell libraries are available.