Manufacturability Optimized Tile

Increasing Manufacturability and Density

Lightspeed Logic is working with our licensees to deliver full-custom based logic tiles. Reconfigurable Logic based on our Manufacturability Optimized Tiles provide optimum results over a wider range of design styles. Considering the case of a device that embeds customer IP as an example, one can understand that the associated RTLs to be mapped onto the fixed logic structure might have a wider range of design styles and design needs. Manufacturability Optimized Tiles address this by allowing drive-strength mutability as well as the ability to have some percentage of the cells being used for flip-flops to be used for combinational functions when not needed as a sequential function.

Because of the regularity provided by the tiling structure and the full knowledge of the immediate neighborhood of the tile, Lightspeed Logic, in partnership with its customers, is deploying OPC/RET technologies in the tile design. As a result both lithography-related variability and stress-related variability are substantially reduced and the timing modeling does not need to accommodate overly pessimistic guardbanding. This work is done on the Manufacturability Optimized Tile when it is created, eliminating DFM problems on Metal-1 and below on the Reconfigurable Logic portion of the die and freeing the design team to focus on design issues instead of DFM related issues. The reduced timing guardbanding results in better achievable performance per watt.

Contact sales@lightspeed.com for additional information.