Inspiration

Lightspeed Logic IP enables new capabilities for SoC design.

For companies who provide ASSPs: have you been using all-mask tapeouts when a metal-only tapeout would have delivered product to the market faster and with lower cost? Have you put more functionality into the device to support multiple markets — even though none of your customers use all of the functionality? Would you be interested in creating product families using only one all-mask tapeout?

For system companies: have you been using an all-mask tapeout approach to ASICs that support multiple system platforms? Has this been causing a negative time-to-market impact due to having to verify all of the functionality on the chip — even though most of the system platforms didn’t need all of the functionality? Do you encounter situations in which you use ASSP content in your systems, but you would be able to better differentiate your products if you had been able to embed some of your intellectual property into the ASSP?

For consumer product companies: are you interested in finding ways to accelerate your time to market by four to twelve months?

A New Approach for SoC Design

For these situations and beyond, Lightspeed Logic mask-reconfigurable logic arrays provide the solution you need. Lightspeed Logic’s Reconfigurable Logic enables flexible platforms, the ability to embed customer IP, and more — without changing any of your current tapeout validation. Using our standard tile-based reconfigurable logic, based on your standard cells, your 3D-extraction, timing verification, etc., have no knowledge that the design was mapped onto a regular logic structure.