STMicroelectronics and Lightspeed Logic

STMicroelectronics SPEAr™ Plus600 Customizable Processor uses Lightspeed Logic’s Reconfigurable Logic IP in order to provide STMicroelectronics’ customers with a cost-effective solution which:

• Manages ever-increasing semiconductor complexity
• Addresses market fragmentation — greater number of chips with lower volume each
• Generates ASIC-like die size
• Overcomes NREs which double per generation
• Achieves rapid time-to-market

The SPEAr™ Plus600 features 600K gates of Reconfigurable Logic and 2 ARM926 cores at 333 MHz.

More information at www.st.com

Lightspeed Logic’s Reconfigurable Logic IP is used to implement 600K routable gates of mask- reconfigurable logic in the SPEAr™ Plus600 processors.  The Reconfigurable Logic supports near standard cell density and performance.  The SPEAr™ Plus600 customer is able to add its own proprietary logic to the SPEAr™ Plus600 device, thus achieving ASIC-like differentiation and unit cost with greatly reduced NRE.  The cycle time for new devices is weeks rather than months.